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Alif Semiconductor /AE512F80F55D5AS_CM55_HP_View /ETH /ETH_AXI_LPI_ENTRY_INTERVAL

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Interpret as ETH_AXI_LPI_ENTRY_INTERVAL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LPIEI

Description

AXI LPI Entry Interval Register

Fields

LPIEI

LPI Entry Interval Contains the number of system clock cycles, multiplied by 64, to wait for an activity in the ETH module to enter into the AXI low power state. 0x0 indicates 64 clock cycles

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THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data